As the gate length in transistors shrinks in order to keep pace with demands for improved performance, the thickness of the gate electrode and the gate dielectric layer are following a trend toward thinner films. Shrinking device dimensions force a thinner dielectric layer in order to maintain an adequate capacitance between the gate electrode and the channel region. Traditional gate dielectric layers consisting of silicon oxide with a dielectric constant of about 4 have reached a minimum limit for thickness at about 1 nm. Below that thickness, a tunneling current problem cannot be avoided.
A typical transistor is shown in FIG. 1 and is comprised of a substrate 1 with isolation regions 2 that separate an active region 10 from adjacent devices. A gate dielectric layer 3 and a gate electrode 4 are formed on the substrate 1. There are lightly doped source/drain (LDD) regions 5 otherwise known as source/drain extensions that are formed below sidewall spacers 6 on opposite sides of the gate electrode 4. Deep source/drain regions 7 are located between the source/drain extension regions 5 and isolation regions 2. The channel 8 is located beneath the gate electrode and between source/drain extension regions 5. Silicidation is usually performed to provide suicide regions 9 above the gate electrode 4 and above the deep S/D regions 7.
Silicon oxide in the gate dielectric layer 3 is being replaced by high k dielectric materials such as Ta2O5, ZrO2, and HfO2 with a k value of greater than 20. A high k dielectric layer 3 may have a larger thickness than a silicon oxide layer and still provide equivalent or improved performance. Thus, high k dielectric materials provide a path to scaling the effective oxide thickness (EOT) in gate dielectric layers to less than 2 nm in advanced technologies.
One problem associated with high k dielectric layers is that they are not easily removed from over isolation regions or over areas of the substrate that will become source/drain (S/D) regions. Conventional plasma etch methods do not provide a high enough selectively for ZrO2 or HfO2, for example, relative to SiO2 above isolation regions or relative to silicon above S/D regions in the substrate. Furthermore, ZrO2 and HfO2 have an etch rate that is too slow to be useful in the buffered HF treatment that is effective in removing silicon oxide. Therefore, a method that is able to selectively remove HfO2, ZrO2, or other high k dielectric materials at a sufficient rate that is applicable to manufacturing is needed. Moreover, the method should not form high k dielectric etch residues which are difficult to remove.
U.S. Pat. No. 6,306,715 describes a method for isotropically etching a metal oxide such as HfO2. A combination of SF6, Cl2, and O2 or a mixture of Cl2 and O2 is used to create an undercut profile beneath a gate to allow for angled ion implant and to prevent polybridging.
U.S. Pat. Nos. 6,300,202 and 6,432,779 to Motorola provide for a method of removing a high k dielectric layer such as Ta2O5, ZrO2, and HfO2 by reducing the metal oxide to a metal or to a metal hydride which is then etched by an acid solution. However, the reducing ambient of hydrazine at 800° C. might also react with other parts of the device.
Other related art in U.S. Pat. No. 6,297,539 describes a means of improving the electrical properties of ZrO2 and HfO2 by doping with a trivalent metal. The deposition step is followed by annealing at 400° C. to 900° C. However, the patent does not mention a process for removing the doped films.